The invention relates to a printed circuit board tester including an electronic analyzer and a grid pattern of contact points arranged in a regular pattern in a grid pattern plane. The contact points of the grid pattern are electrically connected to said electronic analyzer such that test points of a circuit board to be tested can be electrically scanned, whereby several contact points of said grid pattern are electrically interconnected. The circuit board is connectable to said contact points of said grid pattern by means of an adapter and/or a translator.
One such printed circuit board tester is known from EP 0 875 767 A2. This tester comprises a grid pattern on which an adapter and/or a translator is mounted on which a circuit board to be tested may be placed. The adapter and/or translator produces an electrical contact from the circuit board test points of the board under test to the contact points of the grid pattern. The contact points of the grid pattern are electrically connected to the test connections of an electronic analyzer so that each circuit board test point can be accessed by the electronic analyzer.
In this known tester several contact points of the grid pattern are electrically interconnected and are in each case in contact with a single test connection. As a result, the number of units of the electronic analyzer as compared to conventional circuit board testers is drastically reduced since each electronic unit permits access to a multiple of the contact points of the grid pattern. When, for example, arrays of 10 contact points of the grid pattern are to be electrically interconnected, then 10 times as many contact points can be accessed with an electronic unit than with conventional printed circuit board testers.
The electrically interconnected contact points of an array are arranged distributed over the grid pattern. This is the only way of assuring that no terminal contact is doubly assigned such that two circuit board test points are electrically connected to a common terminal contact.
The contact points of the grid pattern are configured on a multilayer circuit board. The layers of the multilayer circuit sandwich the tracks. The scan channels electrically interconnect the contact points.
This known printed circuit board tester has a proven record of success and features substantial advantages as compared to conventional testers. Fabricating the multilayer circuit board on which the contact points of the grid pattern are configured is, however, complicated since a plurality of scan channels needs to be incorporated. All of the scan channels must be faultless such that there must be no short-circuit to another scan channel and no scan channel must have an open-circuit. Fabrication in the case of a large-area grid pattern becomes expensive and extremely technically complicated, demanding highly sophisticated know-how.
There is thus a need for such a printed circuit board tester in which the contact points of the grid pattern are electrically interconnected that is nevertheless simple and thus cost-effective to fabricate.
DE 37 17 528 A1 describes a printed circuit board tester comprising a center-spacing adapter consisting of a stacked pack of circuit boards. Each circuit board is insulated from the other. Each circuit board is provided on one face with output contacts and two further opposing faces being provided with input contacts. The faces provided with the input contacts face two separate pattern arrays of test contacts. These test contact pattern arrays have a larger center-spacing than that of the output contacts. The object of this center-spacing adapter is to reduce the wide center-spacing of the terminal contact pattern arrays to the tight center-spacing of the circuit board test points.
EP 0 331 614 A1 relates to a printed circuit board tester adapter made up of several segments. Each segment consists of two circuit boards sandwiching contact pins. The contact pins are provided for contacting the printed circuit board test points and are electrically connected to the contact elements by means of tracks and plated through-holes incorporated in the circuit boards. These contact elements, which protrude from the side opposite the contact pins at each segment, are arranged with a larger center-spacing than that of the contact pins and serve to contact a contact array of an analyzer.
EP 0 263 244 A1 describes a printed circuit board tester including several driver boards. Each driver board comprises a contact array plug arranged juxtaposed in the tester so that the contact pins protruding from the contact array plugs form a uniform grid pattern. Arranged above this grid pattern are upright strip-like receptacle contact array members. Each contact array member is provided with a plurality of holes mounting spring elements. A test pin is inserted into each spring element so that it is electrically connected to the contact pins via the spring elements. The contact pins in turn are electrically connected to the driver board by wiring.
EP 0 145 830 A1 relates to a contact array for a printed circuit board tester. The contact array is formed by a number of driver cards arranged juxtaposed in parallel provided at one end with a contact plug in which the contact pins for contacting the circuit board test points are arranged. These contact plugs are arranged juxtaposed so that a uniform pattern of contact pins is configured.
DE 33 40 179 C1 describes a center-spacing adapter for translating an initial pattern on a large center-spacing to a final pattern having a close center-spacing. For this purpose two reduction planes are provided in which upright strip-like circuit boards are arranged densely packaged juxtaposed. Each of the circuit boards is provided with tracks whose center-spacing increases in the direction of the initial pattern, thus resulting in the tight center-spacing of the final pattern being formed on the larger center-spacing of the initial pattern.
The invention is an improvement of the aforementioned printed circuit board tester to enable it to be fabricated and serviced simpler and cheaper.
The printed circuit board tester in accordance with the invention comprises an electronic analyzer and a grid pattern of contact points arranged in a regular pattern in a grid pattern plane. The contact points of the grid pattern are electrically connected to the electronic analyzer such that test points of a circuit board to be tested can be electrically scanned, whereby several contact points of the grid pattern are electrically interconnected. The circuit board is connectable to the contact points of the grid pattern by means of an adapter and/or a translator.
The tester in accordance with the invention includes several grid bases, each of which comprises a contact point narrow side surface at which the contact points are arranged. The grid bases are provided with tracks. Each track is electrically connected to several contact points. In addition, each track includes an electric terminal connection leading to a terminal contact for connecting the electronic analyzer so that several contact points are electrically connected to a terminal contact. The grid base circuit boards are arranged with their contact point narrow side surfaces in the grid pattern plane for configuring the grid pattern.
Due to the configuration of the printed circuit board tester in accordance with the invention, the grid pattern is not formed by a single circuit board. The contact points of the grid pattern instead are arranged at the contact point narrow side surfaces of the grid bases such that a plurality of grid bases form by their contact point narrow side surfaces, a surface area not necessarily integral in which the grid pattern is configured. By providing the grid bases, the tracks interconnecting the contact points can now be arranged distributed over the full surface area of the grid bases. This substantially facilitates their fabrication as compared to the configuration of the grid pattern on a multilayer circuit board as described in the prior art. In the prior art, the scan channels are configured in the individual layers as thin conductor wires located very closely to each other. With the grid bases in accordance with the invention, the tracks can now be provided substantially wider since the space available in this case is merely restricted by the center-spacing of the grid pattern and the size of the grid bases which is practically optionally selectable.
The grid bases stand preferably upright on the grid pattern plane. In an alternative embodiment, the grid bases can be arranged inclined to the grid pattern plane. The contact point narrow sides surfaces are then configured correspondingly inclined to the side surfaces of the grid bases so that they form a flat surface area on which an adapter and/or a translator can be placed.
Preferably the grid bases are configured multilayer. Each layer is separated from the other by an electrically insulating interlayer 16. Each of the contact points is electrically connected to a contact point track extending transversely to the contact point narrow side surfaces. Several bus tracks extending transversely to the contact point tracks are provided on one surface of a layer on which no contact point tracks are arranged. Each of which is electrically connected to one of the bus tracks by means of a plated through-hole so that the plurality of contact points is thus guided with the contact point tracks to a relatively small number of bus tracks. These bus tracks produce the electric connection between several of the contact point tracks. The terminal contacts for the electronic analyzer may be provided both on the bus tracks and on a corresponding number of contact point tracks. The arrangement of the electrically interconnected contact points of the grid pattern is dictated by the arrangement or pattern of the plated through-holes on the grid bases. This is because the arrangement of the plated through-holes defines which bus track is electrically connected to which contact point track and accordingly to which contact point of the grid pattern. Producing such plated through-holes is technically no problem and thus the arrays of electrically interconnected contact points are defined by simple ways and means.
In one preferred embodiment the terminal contacts of differing grid bases are electrically interconnected by means of a link board. Connecting the link board are electronic units of the electronic analyzer which are electrically connected to the terminal contacts of the grid bases via the tracks of the link board.
In another embodiment the bus tracks may be provided with bus contact points whereby several bus contact points may be electrically interconnected so that the contact points of differing grid bases are electrically interconnected. For electrically connecting several bus tracks, a link board is preferably used which can be placed on the bus contact points.